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Mon Aug 20 15:40:01 EDT 2018

Next? Verilog

Verilog gen so PLL can be tested + mem init.

Some other things need cleanup before that.  And now is not the time.
Too much "work-like".

Is output propagation for "Connect" still necessary?

One way to do this though is to create Verilog2 as a print of 
[(Vertex, (SSize, Expr Vertex))]

Then use postprocessing later to fix things.

EDIT: This is still a big step.  I need an analysis routine to filter
out memories, which are modeled as combinatorial network + delay.

EDIT: Currently, type information of constants is lost.  So keep tracking that.

EDIT: Fanout of Memory node is []?
First, clean up types a bit.

This is the graph.

(35,TypedForm {typedFormType = Just 16, typedFormForm = Memory 26 29 28 95},[])
(36,TypedForm {typedFormType = Just 16, typedFormForm = Delay 35 0},[38])

Fanout is 0 because delays are not counted.

Is it possible to keep the full graph representation, and turn it into
a DAG when needed?

EDIT: Created se printer, then disabled that as default.  Running into this error:


EDIT: Memory -> Delay fanout is now accessible again:

(35,TypedForm {typedFormType = Just 16, typedFormForm = Memory 26 29 28 95},[36])
(36,TypedForm {typedFormType = Just 16, typedFormForm = Delay 35 0},[38])


 memory_decl: ((2,TypedForm {typedFormType = Just 16, typedFormForm = Memory 33 34 35 4}),
               (3,TypedForm {typedFormType = Just 16, typedFormForm = Delay 2 0}))



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