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Sat Aug 18 09:34:02 EDT 2018

Verilog debugging

Trying to generate f_soc with Verilog.hs
Running into things like this:

wire [99:0] s144; // "s144" <- (IF "rx_in" (CONST _:0) (CONST _:1))

Solution?  This needs to be constant-folded.
For now it's probably OK to leave it in as yosys will optimize it out.

The real issue here is types: there is no unification going on in the
other direction.

I'm shuffling things around so a workaround can be added to f_soc.hs

EDIT: still there

f_soc: fix_binding:
("s144",Comb3 (SInt Nothing 0) 
 IF (Node (SInt (Just 1) 0) "rx_in") (Const (SInt Nothing 0)) (Const (SInt Nothing 1)))


Hack: it's possible that these disappear when bundling expressions.
But the best solution is to perform a unification pass on all the bit
types in SeqTerm.




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