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Fri Aug 17 22:01:21 EDT 2018

RTL

Yosys manual: 2.1.4 Register-Transfer Level (RTL)

  Many optimizations and analyses can be performed best at the RTL
  level.  Examples include FSM detection and optimization,
  identification of memories or other larger building blocks and
  identification of shareable resources.

multi-level logic synthesis

- Binary-Decision-Diagram (BDD) has a unique normal form.
https://en.wikipedia.org/wiki/Binary_decision_diagram
This is nested IF / 2-1 multiplexers.

- And-Inverter-Graph (AIG) better worst case performance. ABC uses this.
https://en.wikipedia.org/wiki/And-inverter_graph




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