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Fri Aug 17 16:17:14 EDT 2018

Verilog

One reason to generate Verilog is to make it easier to do direct
instantiation.

EDIT: I'm thinking that the other direction might actually be a lot
more important: take a verilog module, and instantiate it into Seq.
The simplest way is maybe to use yosys or icarus to translate it to a
netlist.  This can probably be done lazily, once there is a need.

EDIT: Verilog generation is complete.  Needs some testing still.
Import, I'd like to see if I can do something with blif.

http://www.clifford.at/yosys/files/yosys_appnote_010_verilog_to_blif.pdf

Looking at what kinds of gates are in the blif:

tom@panda:~/asm_tools$ cat f_soc.blif |grep ^.gate | awk '{print $2}'|sort|uniq
SB_CARRY
SB_DFF
SB_DFFE
SB_DFFER
SB_DFFESR
SB_DFFESS
SB_DFFR
SB_DFFSR
SB_DFFSS
SB_LUT4
SB_RAM40_4K





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