Fri Aug 17 12:34:54 EDT 2018

Bit serial architecture.

These could be cycled through a RAM, giving 16 registers of 256 bits

I'm actually really intrigued by this.  Seems like a perfect task for
a good macro language!

But, let's cut it short: before building something like this, build a
fixed datapath DSP.  A FIR or a biquad.  Once it is clear how to
abstract it, only then move on to CPU design.

EDIT: The instruction word and decoder will have to be parallel.  The
argument could be streamed in.  Next instruction address can be
streamed out as part of the ALU.  It seems that the main design
challenge is to design the ALU.  Routing needs to be determined from
the instruction word.  Operations like conditional jumps need an extra
cycle to decide between continue and jump.  Probably simplest to do it
in two macro cycles: compute condition and jump in the next cycle.