[<<][rtl][>>][..]
Fri Aug 17 08:39:05 EDT 2018

Next

- Direct Verilog RTL code gen.
- Type-level additions
- Syntax preprocessor
- Get rid of (SInt (Just n) _) and use e.g. Reg t v , Sig t , Const v

None of these are essential.

SInt can be left if replaced by a wrapper like sbits.  EDIT: Did that.
Simplifies things without making a huge change.

Type directed stuff: I'm asking for help on Twitter.

Syntax preproc.  Seems to be more trouble than it's worth because this
needs "escapes" for generic meta-level stuff.  It seems that just
sticking to "do" for now is the best option.  Maybe some TH can help
as a middle ground?

Verilog seems most useful to cut out MyHDL entirely.  It's nice, but
not really necessary.  And I'm not using it's main purpose: to be able
to use Python as a macro and test bench language.

EDIT: Started putting in the boilerplate for Verilog.hs
It seems quite straightforward, boring.




[Reply][About]
[<<][rtl][>>][..]