[<<][rtl][>>][..]
Thu Aug 16 18:52:47 EDT 2018

Lessons Learned

1) You can't escape the fact that you're dealing with circuits.

2) Resource sharing is about multiplexing.

3) Generated Verilog can be simple (just RTL).

4) Monadic do notation is still awkward, and there do not seem to be
   any obvious workarounds.




[Reply][About]
[<<][rtl][>>][..]