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Thu Aug 16 16:30:26 EDT 2018

Generate verilog directly

This could just be straight up RTL.

module <name> ( <signal> ... ) {
input <signal>; ...
output <signal>; ...
wire [<size-1>:0] <signal>;
reg  [<size-1>:0] <signal>;
assign <signal> = <combinatorial_expression>;
}

Then the sequential bit could be one big block.




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