Thu Aug 16 11:35:36 EDT 2018
FPGA SPI bug
Here's the theory: the sampling edge is 0->1, but the initial clock
phase is 1. The FPGA is immune to this, but my edge detector is not.
Let's just look at the scope. Nah I need to solder...
So let's look at the iceprog code. This is how it starts a transfer
when in MPSSE modes.
send_byte((n-1) >> 8);
The code here is more readable:
#define MPSSE_WRITE_NEG 0x01 /* Write TDI/DO on negative TCK/SK edge*/
#define MPSSE_DO_WRITE 0x10 /* Write TDI/DO */
So it writes the data on the negative edge.
Which means the initial polarity is 1.
Now, make a test for SPI phase.
Basically, specify this properly.