[<<][rtl][>>][..]
Tue Aug 14 22:34:27 EDT 2018

Bad hex value 1ff

def _convertInitVal(reg, init):

_toVerilog.py 


def _convertInitVal(reg, init):
    if isinstance(reg, _Signal):
        tipe = reg._type
    else:
        assert isinstance(reg, intbv)
        tipe = intbv
    if tipe is bool:
        v = '1' if init else '0'
    elif tipe is intbv:
        v = "%s" % init if init is not None else "'bz"
    else:
        assert isinstance(init, EnumItemType)
        v = init._toVerilog()
    return v

init is originally set to the string "1ff"

type(init) is <class 'myhdl._modbv.modbv'>

and converted to string it is 1ff

I guess that's the problem?

Implementation of this is in _intbv.py

EDIT: fixed it by

-        v = "%s" % init if init is not None else "'bz"
+        v = "h%s" % init if init is not None else "'bz"



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