Tue Aug 14 15:40:27 EDT 2018


Everything is there to create a test bench for the soc to run in
MyHDL, and to then run it on the hardware.

What should this do?  Likely best to take the application mainloop.

Currently what's in the way is the ability to upload SPI code to the
running FPGA.  I need to really go ahead and do this.

And I really don't want to?  Why is that?

Because it is all so hard to debug.  Can I make that easier?  Can I
make an always-on logic analyzer?  Let's set that up instead.

It's the software.  I don't want to run a daemon and I don't want to
have it streaming data constantly.

What I want is the following:

- Send status once per second or per request
- Send status on change

Do this for all GPIOs.
Use a dedicated blue pill board.

EDIT: This is madness.  Decision fatigue. I put everything together
but stopped.  I could just solder up the board and do it manually.
Why is it so hard to start doing that?

I guess I'm just tired.