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Tue Aug 14 10:09:55 EDT 2018

MyHDL code gen cleanup

Create a single generator.

Currently there are 3:

toPy
testbench
fpga


I need one interface.  The problem is that there are a couple.


m [r S]            passed into compileTerm
[r S] -> m ()      mirrors MyHDL port api
[r S] -> m [r S]   mirrors Seq processor

What is needed?

- FPGA code generation

- Test benches


The problem is with the latter.

So let's focus on code gen first, then figure out a way to implement
i->o test benches.

EDIT: got it sorted out + can execute from haskell, though it needs
intermediate files.



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