[<<][rtl][>>][..]
Mon Aug 13 16:16:04 EDT 2018

Memory instantiation hierarchy problem

I don't understand what's going wrong here.

Traceback (most recent call last):
  File "run_myhdl.py", line 140, in <module>
    load_and_run(sys.argv[1], sys.argv[2])
  File "run_myhdl.py", line 134, in load_and_run
    toVerilog(hdl_fun, env, *signals)
  File "/home/tom/priv/git-private/humanetics/gw_src/deps/asm_tools/myhdl/myhdl/conversion/_toVerilog.py", line 176, in __call__
    siglist, memlist = _analyzeSigs(h.hierarchy)
  File "/home/tom/priv/git-private/humanetics/gw_src/deps/asm_tools/myhdl/myhdl/conversion/_analyze.py", line 92, in _analyzeSigs
    assert(delta >= -1)
AssertionError

I think I understand.  Signals need to be passed in from the top or
created at the same level.  They cannot be instantiated at lower
levels and bubbled up.



Trying to fix it


	s14_rd = Signal(modbv(0)[1:0])
	s14_we = Signal(modbv(0)[1:0])
	s14_wa = Signal(modbv(0)[1:0])
	s14_wd = Signal(modbv(0)[1:0])
	s14_ra = Signal(modbv(0)[1:0])
	inst1 = ram.ram(CLK, s14_wa, s14_wd, s14_we, CLK, s14_ra, s14_rd)        


	s14_rd = env.sig(16, 0)
	s14_we = env.sig(1, 0)
	s14_wa = env.sig(8, 0)
	s14_wd = env.sig(16, 0)
	s14_ra = env.sig(8, 0)
	inst1 = env.ram(CLK, s14_wa, s14_wd, s14_we, CLK, s14_ra, s14_rd)        



[Reply][About]
[<<][rtl][>>][..]