Mon Aug 13 09:17:29 EDT 2018
Move it forward.
- MyHDL memories
- MyHDL simulation
- FPGA through FTDI upload
- FPGA wire-up
EDIT: I got it up to this point:
[s14_rd, s14_we, s14_wa, s14_wd, s14_ra] = s14
from mem bus:
s17.next = ((s14_rd) if s13 else 0)
to mem bus:
s14_we.next = 0
s14_wa.next = 0
s14_wd.next = 0
s14_ra.next = s59
What's needed is some types to plug into the instantiation, and
possibly a decoupling through passing env?
[s14_rd, s14_we, s14_wa, s14_wd, s14_ra] = env.memory("s14", 8, 16)
This way the instance itself doesn't need to be handled inside the
Then do the same for signal?
EDIT: Probably best to create the instance and pass it on.
- Find addr,data sizes + add to instances.
- Renames from probes