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Sat Aug 11 13:31:30 EDT 2018

CPU hierarchy

I've got the basic idea patched up.  Decomposed into a couple of levels:

- top level io
- bus peripherals on bus
- cpu sequencer + memory
- instruction decoder

Ha.. that's why they are called peripherals!  They sit between the CPU
and the outside world.


So this is great.  Once that basic structure is there, the rest is
incremental.

Next: make a uart read/write test, or just the 2 main loops of the
application.  Uart write and some i/o and timing control.




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