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Sat Aug 11 11:19:41 EDT 2018

Busses, cont

With a bus, these are the basic instructions:
- jmp
- read  (bus->reg)
- write (reg->bus)
- im    (ins->reg)

But there still is no synchronization.  I need a blocking read.

Instead of using a register interface, what about using a port interface?
But a register read is already needed.

What I miss is a direct flag input.  This could still be part of the
bus.

The missing bit is really the read operation.  I'm thinking of this as
one thing, but it is actually always split over two cycles:

- issue read
- wait for read to be stable on the bus

This could be the next instruction, but it might be a later one as well.

With this in mind, look at an example bus: Wishbone
https://en.wikipedia.org/wiki/Wishbone_(computer_bus)

This seems overkill.

What I need is just a read ready signal such that the cpu can read
from a stream.

Another important realization is that a bus is simpler when it has a
master and a slave side, and needs special attention when these roles
need to switch.




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