Sat Aug 11 08:03:08 EDT 2018
Focus more on composition
I now have fifo interfaces and ser/deser. How to compose these on a
The problem is still sequencers. How to abstract those better?
Maybe start from the top this time. Build the loop controller for the
application and see where that gets stuck.
So here's a nice goal for today: get a basic CPU-like sequencer
running on FPGA, producing an output loop.
Maybe what I've been overlooking is the explicit construction of a
bus, so let's start there.