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Fri Aug 10 11:04:36 EDT 2018

Check yosys output

This is actually more important.  So the thing to do is to get
everything to run on FPGA and see if Yosys can optimize what Seq
produces.

What to use?  Maybe the UART makes sense?  That's something I can just
monitor easily.

EDIT: I have no way to judge this output..

EDIT: Was wrong - was doing just logic opti.  Doing the ice40_synth
does give something that doesn't look too bad.  PNR phase says:

After packing:
IOs          4 / 206
GBs          0 / 8
  GB_IOs     0 / 8
LCs          27 / 7680
  DFF        11
  CARRY      5
  CARRY, DFF 0
  DFF PASS   0
  CARRY PASS 2
BRAMs        0 / 32
WARMBOOTs    0 / 1
PLLs         0 / 2


EDIT: It optimized out the shift register because I'm using only one
bit.  Here's with all 8 outputs routed out of the FPGA:


After packing:
IOs          11 / 206
GBs          0 / 8
  GB_IOs     0 / 8
LCs          34 / 7680
  DFF        18
  CARRY      5
  CARRY, DFF 0
  DFF PASS   7
  CARRY PASS 2
BRAMs        0 / 32
WARMBOOTs    0 / 1
PLLs         0 / 2

Which added 7 more logic cells.  This doesn't look too bad really.

      



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