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Fri Aug 10 11:00:53 EDT 2018

Now here's an other idea.

What about making a language that is more like Verilog, and plug it
into Seq?  I can probably use Yosys to generate a netlist, then
compile that into Seq for unit testing.

Simulation in Haskell is nice, but expressing the primitive state
machines is a bit of a pain.




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