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Sun Aug 5 19:43:00 EDT 2018

Stacks

Looking at swapforth.
https://github.com/jamesbowman/swapforth/blob/master/j1a/verilog/stack2.v

It seems that the stacks are implemented as registers.

This would avoid the delay issue.

Study that some more, and see if it's possible to do actually express
this in Seq.




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