Sun Aug 5 19:33:34 EDT 2018

CPU design

It's starting to get more clear that there are a lot of design choices!

1. multi-clock instruction cycle (e.g. PIC)
2. hazard-mitigation through NOP
3. stall
4. pipelining

What is my goal? To keep it simple, and to have deterministic
execution.  Leaving in the hazards seems best to get a first working