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Sun Aug 5 18:26:24 EDT 2018

Write-through delay for FIFO and stack

Here's a stack implementation:

https://github.com/jandecaluwe/myhdl-examples/blob/master/ChessPlayingFPGA/stack/stack_myhdl.py

For my use case, is it ok if the data is only available on the next
cycle?

1. pop (computes new rAddr)
2. use rData

1. push
2. use rData <- has previous result
3. use rData <- has pushed result

So it seems that write-to-read delay is important.

So I don't actually know if it is an issue.  But if it is, it can
likely be solved later by cleaning up a NOP workaround.




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