Sun Aug 5 13:47:24 EDT 2018

Memory init

Ising FPGA memory as ROM, what is the output of wData on just out of
reset?  Is this an actual combinatorial readout?

Look at the simulator spec.
It doesn't specify a reset value.


Figure 3. EBR Module Timing Diagram 1

So it clearly says the data is only valid after the first read address
has been clocked.

To use this as instruction memory, either:
- ignore the first read (e.g. reset value = 0)
- use a run enable signal to ensure the first instruction is read

Practically, the CPU will be loaded by another one, so I'm assuming
the run signal is explicit.  Otherwise, use a single delay to start

See memory usage guide for ice40
To push this to verilog, have myHDL insert something like:

defparam ram256x16_inst.INIT_0 =