Thu Aug 2 11:36:20 EDT 2018

Behavioral vs. RTL

I've never really understood the distinction here, and it appears that
there is no clear-cut distinction.


Reading Yosys manual, the distinction is made between

  - register update
  - if / case
  - unrollable loop

  - combinatoral networks
  - registers

So the distinction is really not that important for Seq approach.
Behavioral bits are implemented as macros.

  ... modern logic synthesis tools utilize much more complicated
  multi-level logic synthesis algorithms. Most of these algorithms
  convert the logic function to a Binary-Decision-Diagram (BDD) or
  And-Inverter-Graph (AIG) and work from that representation.

Yosys uses ABC


RTLIL is used for internal optimizations.  It does seem to perform
some high-level optimizations and recognition steps, so maybe it does
make sense to keep the input syntax in some partitular form.

It's not quite clear if that yosys-specific optimization stuff is
really needed if ABC is used.

The way to find out is to have it dump some internal representations.