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Thu Jul 19 15:08:27 EDT 2018

more UART

Sending out 5.  Why does it see 5<<1 | 1

The sample pulses are fine.  But it is clocking in the bit when the
bit changes.

It works when the register output is taken.

EDIT: Important: do not propagate the _input_ of registers that use
clock enable.


-- 48
[9,1,0,0,0,3]
[9,1,0,0,0,3]
[9,1,0,0,0,3]
[9,1,0,0,0,3]
[9,1,0,0,0,3]
[9,1,0,0,0,3]
[9,1,0,0,0,3]
[9,1,0,0,0,3]
-- 49
[8,0,0,0,1,3]
[8,0,0,0,1,2]
[8,0,0,0,1,1]
[8,0,0,0,1,0]
[8,0,0,0,2,63]
[8,0,0,0,2,62]
[8,0,0,0,2,61]
[8,0,0,0,2,60]
-- 50
[8,0,0,0,2,59]
[8,0,0,0,2,58]
[8,0,0,0,2,57]
[8,0,0,0,2,56]
[8,0,1,0,2,55]
[16,0,0,0,2,54]
[16,0,0,0,2,53]
[16,0,0,0,2,52]
-- 51
[16,0,0,0,2,51]
[16,0,0,0,2,50]
[16,0,0,0,2,49]
[16,0,0,0,2,48]
[16,0,1,0,2,47]
[32,0,0,0,2,46]
[32,0,0,0,2,45]
[32,0,0,0,2,44]
-- 52
[32,0,0,0,2,43]
[32,0,0,0,2,42]
[32,0,0,0,2,41]
[32,0,0,0,2,40]
[32,0,1,0,2,39]
[64,0,0,0,2,38]
[64,0,0,0,2,37]
[64,0,0,0,2,36]
-- 53
[64,0,0,0,2,35]
[64,0,0,0,2,34]
[64,0,0,0,2,33]
[64,0,0,0,2,32]
[64,0,1,0,2,31]
[128,0,0,0,2,30]
[128,0,0,0,2,29]
[128,0,0,0,2,28]
-- 54
[128,0,0,0,2,27]
[128,0,0,0,2,26]
[128,0,0,0,2,25]
[128,0,0,0,2,24]
[128,0,1,0,2,23]
[0,0,0,0,2,22]
[0,0,0,0,2,21]
[0,0,0,0,2,20]
-- 55
[1,1,0,0,2,19]
[1,1,0,0,2,18]
[1,1,0,0,2,17]
[1,1,0,0,2,16]
[1,1,1,0,2,15]
[3,1,0,0,2,14]
[3,1,0,0,2,13]
[3,1,0,0,2,12]
-- 56
[2,0,0,0,2,11]
[2,0,0,0,2,10]
[2,0,0,0,2,9]
[2,0,0,0,2,8]
[2,0,1,0,2,7]
[4,0,0,0,2,6]
[4,0,0,0,2,5]
[4,0,0,0,2,4]
-- 57
[5,1,0,0,2,3]
[5,1,0,0,2,2]
[5,1,0,0,2,1]
[5,1,0,0,2,0]
[5,1,1,0,3,7]
[11,1,0,0,3,6]
[11,1,0,0,3,5]
[11,1,0,0,3,4]
-- 58
[11,1,0,0,3,3]
[11,1,0,0,3,2]
[11,1,0,0,3,1]
[11,1,0,0,3,0]
[11,1,0,1,0,0]
[11,1,0,0,0,3]
[11,1,0,0,0,3]
[11,1,0,0,0,3]
-- 59
[11,1,0,0,0,3]
[11,1,0,0,0,3]
[11,1,0,0,0,3]
[11,1,0,0,0,3]
[11,1,0,0,0,3]
[11,1,0,0,0,3]
[11,1,0,0,0,3]
[11,1,0,0,0,3]




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