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Wed Jul 18 00:00:24 EDT 2018

MyHDL case statements

http://docs.myhdl.org/en/stable/manual/conversion.html

If-then-else structures may be mapped to case statements

    Python does not provide a case statement. However, the converter
    recognizes if-then-else structures in which a variable is
    sequentially compared to items of an enumeration type, and maps
    such a structure to a Verilog or VHDL case statement with the
    appropriate synthesis attributes.


I might have to do this differently.  Currently, conditionals are
duplicated at the meta level.  It might be good to re-arrange that
into imperative if then else.


They get inferred differently: priority routing network vs. single mux.

https://electronics.stackexchange.com/questions/73387/difference-between-if-else-and-case-statement-in-vhdl

I do wonder: in the case the inputs are exclusive, does the
combinatorial optimization figure this out?




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