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Mon Jul 16 17:48:24 EDT 2018

VHDL and synthesis

https://web.ewu.edu/groups/technology/Claudio/ee430/Lectures/vhdl-guidelines.pdf

Mostly boils down to:
- do not create latches
- beware of duplication
- some things are not synthesizable

I'm encouraged in the approach
- to make registers explicit
- to model combinatorial networks as functions




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