Mon Jul 16 16:26:43 EDT 2018
if' works only on signals. not on containers of signals!
to make it work on containers, it needs to be lifted:
forall m r. Seq m r =>
SType -> r S -> m (r S)
async_receiver t i = closeReg [bit,t] update where
update [is_on, n] = do
on <- return [i, is_on, n] -- dummy
off <- return [i, is_on, n] -- dummy
(o:s') <- sequence $ zipWith (if' is_on) on off
Note that this is quite different from how MyHDL can have if branches
that contain assignments.
So I am _intentionally_ building a dataflow subset. The parallel
nature of if muxes is quite explicit that way.
Does this need special care for non-binary muxes?