Mon Jul 16 10:47:01 EDT 2018

Clocks, RTL

So two way to look at digital cicuits:

1) Go from event-driven to sequential

2) Still, in the sequential domain, there is a need to represent
signals that are somehow "clocked".  The way to do this is to
synchronize to the sampling clock, and add an enable bit.

Basic intuition here is that for FPGA design, signal flow needs to be
directional, which meshes very well with functional programming.