[<<][rtl][>>][..]
Sat Jul 7 08:23:29 EDT 2018

MyHDL sim test

1. Create the Seq circuit with its own test bench.

2. Generate a MyHDL module that can compile to FPGA code, together
   with some MyHDL wrapper code.

3. Same for a test bench


EDIT: After a bit of doodling I end up with this:

- A testbench module has CLK, RST and a number of outputs.
- It is a python module with a function named "module"
- The module can contqain a list named "output"
- If so it is verified against the simulation output

TODO: Wrap this up.


Ok.  One thing that I'd like to figure out, is how to specify output
types for a module.  Currently it is left to the instantiator to
provide I/O signals, but how does it know what to instantiate?

Maybe generate an instantiator in the .py file

EDIT: Anyways, not a huge problem.  Still need to verify if the output
can actually be synthesized to VHDL or Verilog.

EDIT: I really miss not having actual signal names.
EDIT: Ok I have a small TH hack that can be used to resolve this.




[Reply][About]
[<<][rtl][>>][..]