[<<][rtl][>>][..]
Sat Jun 16 17:59:00 EDT 2018

latches / registers and pure functions

https://forums.xilinx.com/t5/Implementation/why-latches-are-considered-bad/td-p/200291

    The output of a combinational circuit is a function of input only
    and the circuit should not contain any internal state (i.e.,
    memory). One common error with an always block is the inference of
    unintended memory in a combinational circuit. The Verilog standard
    specifies that a variable will keep its previous value if it is
    not assigned a value in an always block. During synthesis, this
    infers an internal state (via a closed feedback loop) or a memory
    element (such as a latch).




[Reply][About]
[<<][rtl][>>][..]