Sat Jun 16 17:19:58 EDT 2018

Preinc/postinc access

Trying to get the combinatorial / register split right for pre/post
inc/dec memory read/write.

For some reason, there is something that isn't quite clicking about
how this is supposed to work.  I guess I want to really see a single
cycle instruction memory work on the FPGA.

The read and write happen on rising read/write clocks.
This is the same behavior as a register.

I guess what I'm looking for is a more detailed description of an
SRAM.  To believe it, I guess..

I don't exactly see where the feedback "fix" is located when it comes
to a clocked memory.  That is the main issue here.  For a register it
is simple: one in / one out.  So what is it like for a memory?

There must be some latch in there somewhere.

When in doubt, look at the simulation.  It captures semantics,

    def rtlwr():
        if write_enable:
            memory[write_addr].next = write_data

    def rtlrd():
        read_data.next = memory[read_addr]

So the memory does behave as a register.  fixMem is correct for the
readAddr -> readReg part, but I'm not sure for the write.  EDIT: It
seems OK, but I want to see it.

If readAddr == writeAddr, there should be a two cycle delay.  This is
something that isn't hard to test on actual hardware.

Make some tests for Seq for these corner cases.

test_mem_delay = SeqEmu.traceState ([empty]) m where
  t = SInt Nothing 0
  m = SeqEmu.fixMem [t] $ \[rd] -> do
    c <- counter $ SInt (Just 8) 0
    return ([(1, 0, c, 0)], [c, rd])

--- test_mem_delay

So indeed, delay is two, passing the two registers (read register, and
internal sram modeled as a register).

How to test this on a scope?  If the counter is 8 steps, and bit 2 is
put out, it will show up as quadrature delay.