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Mon Jun 11 10:33:03 EDT 2018

## MyHDL output

```It's probably possible to join all combinatorial assignments in the
first block, and put the sequential ones in the second block.

from myhdl import *
def module(CLK, RST, s0, s1):
s4 = Signal(modbv(0)[8:])
s2 = Signal(modbv(0)[8:])
s10 = Signal(modbv(0)[8:])
s6 = Signal(modbv(0)[8:])
# s1 is an input
@always_comb
def blk1():
s4.next = (concat((s2[7:0]), s1))
@always_seq(CLK.posedge, reset=RST)
def blk2():
s2.next = (s4)
@always_comb
def blk3():
s10.next = (0 if (s4 == 0) else (1 if ((~s4) == 0) else s6))
@always_seq(CLK.posedge, reset=RST)
def blk4():
s6.next = (s10)
@always_comb
def blk5():
s0.next = (s10)
return [blk1, blk2, blk3, blk4, blk5]

to

from myhdl import *
def module(CLK, RST, s0, s1):
s4 = Signal(modbv(0)[8:])
s2 = Signal(modbv(0)[8:])
s10 = Signal(modbv(0)[8:])
s6 = Signal(modbv(0)[8:])
# s1 is an input
@always_comb
def blk1():
s4.next = (concat((s2[7:0]), s1))
s10.next = (0 if (s4 == 0) else (1 if ((~s4) == 0) else s6))
s0.next = (s10)
@always_seq(CLK.posedge, reset=RST)
def blk2():
s2.next = (s4)
s6.next = (s10)
return [blk1, blk2]

just keep the order?

Maybe not... I wonder if this actually works as expected, or if each
combinatorial value really needs to have its own block.  Or maybe a
Signal is not required?

Damn I ran out of steam before it's finished...

It seems that it is possible to use "naked" intbv, e.g.
http://www.antfarm.org/blog/aaronf/2008/03/myhdl_example_avalonst_error_a.html

# (j is large enough to hold any index into intermediate.)
j = intbv(0, min=0, max=2 + len(i_err))
for i in range(len(outputMapping)):
j[:] = outputMapping[i]
o_err.next[i] = intermediate[int(j)]

What question am I supposed to ask?  What is the difference between
Signal(intbv(...))
intbv(...)

EDIT: Difference between cell and value.

For combinatorial networks, it seems that this is not allowed:

@always_comb:
def f_bc:
b.next = a
c.next = b

The following should always work.

@always_comb:
def f_b:
b.next = a

@always_comb:
def f_c:
c.next = b

For combinatorial code, the used values are in the sensitivity list.
Suppose a is the output of a register.  At a clock edge that updates
a, f_b will run, which updates b, then f_c will run which updates c.

It will not be so hard to make a test case for this.

```
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