[<<][rtl][>>][..]
Wed May 30 11:13:51 EDT 2018

Why is there a pipeline delay?

Maybe before figuring this out, simplify the interface to the monad.
It's not necessary to abstract 'val'.  The user can easily do this in
the testbench stub.

Maybe today is not a good day for refactoring.  Get a nap.

However, it seems that I'm introducing a delay by introducing those
registers as actual registers, on top of the delay created by feeding
back the memory's io state.

EDIT: Damn I'm tired but I can't let go of this.

So this is how it should work:
- User stub should use registers
- But memory stub should use the constant output before it is fed back.

I think this can work with the existing setup.

Basically, only the rData register is an actual register.  The memory
is a combinatorial function from the control inputs to rData decoupled
by that register.

EDIT: Yes that was it.  Makes the code a lot simpler too.




[Reply][About]
[<<][rtl][>>][..]