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Fri May 25 20:27:24 EDT 2018

Generate signals

 --- test_edge
(0,Const 4)
(1,Delay 3)
(2,Const 1)
(3,Comb2 ADD 1 2)
(4,Comb2 SLL 0 1)
(5,Delay 4)
(6,Comb2 XOR 4 5)


Maybe a good exercise to write this as an interpreter.  I can see this
problem of turning a network into a function reoccur.

In this case, assume we know 6 is the output.  What do we need to know?

- collect all registers
- compute output function, stop at registers
- compute update function for each register




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