Fri May 25 14:11:39 EDT 2018
To make this work, it is necessary to first understand what Signals
are. Stick to MyHDL as basic semantics.
Somehow I don't really see why signals need to be so complex.
Maybe just stick to what MyHDL does?
At the very least, I need to distinguish between intermediates (wires)
I think I understand. The difference is whether something appears in
a combinatorial or a sequential block.
So we have some context in which we can do bindings.
Semantics of signals:
1) exactly one driver
2) from comb creates a wire that cannot have loops
3) from seq creates a register which can create loops across clock ticks
Let's try to make this basic program work:
counter a b = do
comb $ do
a <-- not b
seq $ do
b <-- b `add` 1
Two blocks, one combinatorial and one sequential, using a uniary and a
Maybe signals can be implicit?
The do notation's <- can be used to create combinatorial signals
Then a 'set' operation can assign a combinatorial signal to a register.
Following through, this code
counter b = do
a <- inv b
b' <- add b $ L 1
set b b'
main = do
printl $ mapToList $ compile $ signal >>= counter
leads to the following network structure:
signal n is driven by driver d.
(0,Reg (Signal 2))
(1,Comb1 INV (Signal 0))
(2,Comb2 ADD (Signal 0) (L 1))
The combinatorial ones are straightforward. The first one says that
signal 0 is driven by a register, who's input is driven by signal 2.
I'm going to rename Reg to Delay, and separate out constants so they
are explicit drivers of signals:
(1,Comb1 INV 0)
(3,Comb2 ADD 0 2)
Making a next iteration where signals are explicitly driven, allowing
both explicit combinatorial and sequential drive.