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Mon Aug 8 12:52:27 EDT 2016

clock buffers

While yosys says GBs / GB_IOs is 0, it is actually arachne-pnr that
will infer clock buffers during routing.

https://github.com/cliffordwolf/yosys/issues/107


promote_globals...
  promoted FPGA_CLK$2, 162 / 162
  promoted FPGA_RESET$2, 86 / 86
  promoted SPI2_SCLK$2, 53 / 55
  promoted $abc$11948$n3, 43 / 43
  promoted spi_cmd_inst_r_nss, 37 / 37
  promoted dti_in_multi_inst_dti_in_inst_1_cinst_dti_framer_circuit_spiClk, 23 / 23
  promoted dti_in_multi_inst_dti_in_inst_0_cinst_dti_framer_circuit_spiClk, 23 / 23
  promoted $abc$11948$n475, 18 / 18
  promoted 8 nets
    3 sr/we
    1 cen/wclke
    4 clk
  8 globals
    3 sr/we
    1 cen/wclke
    4 clk




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