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Sun Jul 24 17:16:50 EDT 2016

Reading from a tristate signal

Produces None in the MyHDL Simulation if it wasn't driven before.
Because initial value is None, this fails when trying to assign the
value to another signal.

Also arachne-pnr has problems.

( ATM I can't get lattice tools to infer RAM so sticking to
yosys/arachne-pnr for now )

Maybe it's best to avoid the whole thing by manually instantiate as
mentioned here?

https://github.com/cseed/arachne-pnr/issues/24

        SB_IO #(
          .PIN_TYPE(6'b 1010_01),
          .PULLUP(1'b 0)
        ) led_io (
          .PACKAGE_PIN(LED5),
          .OUTPUT_ENABLE(outcnt[0]),
          .D_OUT_0(outcnt[1]),
          .D_IN_0(dummy)
        );

Then to use MyHDL, maybe leave the toplevel file as verilog, and
instantiate separate modules?  That would give a patch point to add
any other workarounds.

Maybe the same can be done with the RAM.

First, syntax:

SB is short for SilliconBlue, before bought by Lattice.
SB_IO is the module name.
#() are constant parameters?
led_io is the instance name
() are module parameters
.param(signal)

http://electronics.stackexchange.com/questions/24316/how-do-i-define-a-module-with-a-modified-parameter-in-verilog
module-name #(parameter-assignment) instance-name (module-terminal-list) ;




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