[<<][myhdl][>>][..]
Mon Jun 20 14:12:54 EDT 2016

edges

I'm still not clear on semantics of time - off by one?

For an assignment to .next during:
@always_seq(p.FPGA_CLK.posedge)

is that change-of-value supposed to happen at this posedge, or the
next one?

Say

a.next = b

when are a and b valid?



The semantics of ".next" is derived from the operational semantics of
the discrete event simulator.  The map to HDL then implements a
similar behavior using FFs.

For combinatorial logic:

  - a.next = b

    really means: a = b  (minus some propagation delay)
    this is why there is no feedback allowed

For sequential logic:

  - a.next = b

    really means: the input of the d-ff (a.next) is set to b, which
    can be derived combinatorially from the output of the d-ff



To remember: printing out signals, only ever print out the "now"
values, not the .next values, because the order in which the updates
are run is not specified.

Still it is confusing to work with this.  Maybe to perform test
readouts, always do them in a clock-sensitive process, instead of
manually trying to guess where things are at from the stim process?





[Reply][About]
[<<][myhdl][>>][..]