Wed Apr 27 21:16:40 EDT 2016

Avoiding interfaces

Maybe it is better to avoid interfaces alltogether, and use explicit
port naming at the top level, then gather these in lists in the

EDIT: got it to work following examples in [1].

Basic ideas:

- Keep the toplevel flat.  This gives most control over pin names, as
  those need to be added to the pin constraint file in iCE40 tools.

- Keep the toplevel stupid: only perform connection there.  Since the
  interface is flat, this code will look flat as well.  But at this
  point it is possible to put the top level ports in lists or

- Inner blocks and generators are not hindered by limitations of the
  top level ports.

- When creating lists of signals, use only flat lists, and be sure to
  assign those lists to a local variable.  Hierarchy analysis uses
  those names, but doesn't raise errors when "None" appears in the
  target HDL code.  Structural modeling isn't completely unconstrained

[1] https://github.com/cfelton/minnesota