Tue Apr 26 17:25:18 EDT 2016

Misconceptions and Quirks

M: Cannot use arrays of interfaces as a parameter to a primitive
generator.  The "type error" here is that interfaces are for
structural modeling.

Q: Can't have instances in lists that get collected?  It confuses
hierarchy extraction.  Workaround: use list.append() Should be fixed
by using @block

M: What is the relation between python blocks and generators, and the
resulting VHDL?  Parameters should correspond.  I get garbage.  Maybe
arrays of interfaces are not supported?

M: It is possible to represent a list of interfaces as an interface of
bit vectors.

M: It is possible to collect signals in a list, and iterate over that
list to perform assignments.

M: I miss plain and simple functions inside @always_comb generator
definitions.  It seems this doesn't work, and needs to be solved at
structural level through instantiation.

M: vec(1) vs vec[1] ?