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Thu Feb 4 13:13:50 EST 2016

toVerilog / toVHDL

toVerilog(Module, *signals)

For simulation, the arguments of a module can be any Python object,
but for conversion to VHDL or Verilog these need to be signals.  


Also, the @always_comb seems to produce a process/always block.  Why
not an RTL / dataflow block?




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