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Sat Mar 7 19:13:29 EST 2015

PLL stability

Trying to wrap my head around stability issues in a PLL design.  The
question that comes to mind is: how can it ever synchronize if the
initial phase variation is so large that the filtered can't "catch"
it?  I.e. I understand that a PLL is stable once it is locked, as it
is close to its linear approximation, but how can it lock in the first
place?

How good does the initial guess need to be?

It seems that the simplest PLL has 2 design variables: low pass cutoff
and loop gain.  My case has another one: frequency offset.  It seems
that offset can be a problem if it gets too far away from the locking
range.

From [1] it seems all filters are integrators.


[1] http://cp.literature.agilent.com/litweb/pdf/ads2008/dgpll/ads2008/PLL_DesignGuide_Reference.html
[2] https://electronics.stackexchange.com/questions/86059/what-is-phase-lock-looppll-lock-range-capture-range




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