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Sat Jul 28 21:53:32 EDT 2012

The non-deterministic S/D modulator

The decorrelator mentioned before can be generalized by taking a
fractional bit input, and producing a random output bit based on the
current accumulator.  This is the basic building block for the whole
S/D synth approach.

How to make this well-defined?  I.e. for a deterministic encoder a bit
is generated if a threshold is reached.  This needs to be reformulated.

E.g. if state is 1.00 and input is 1.00, the probability of a 1 bit
should be 100%, which then leaves the state at 50%.

If state is 0 and input is 0, the probability of a 1 bit should be 0%

If state is seeded by 0, and input is 0.50 on every step, by symmetry
the probability of the output should always be 50%.

What about this:
- If state > 1  -> deterministic 1
- If state < 0  -> deterministic 0
- Else -> value = uniform probability for 1

This seems ad-hoc, however the hard limits are really caused by the
hard limits of saturated 0/1 signals.

It sees that in the non-deterministic case, the state needs to be able
to "buffer" an "unlikely 1".  Is there a way to make this buffer
larger to spread it out more?  I would guess there is going to be some
tradeoff in the probability distribution.

E.g. state is 0.01 and input is constant 0.01 which means there is a
1/50 chance the next pulse is a 1.  If it is, then the next 99 pulses
are going to be guaranteed 0.  This seems too rigid.  It is
"correlation due to saturation".  Is it possible to spread out pulses
over a longer period of time?

What is the difference with the decorrelator?  It has an n-bit bucket
(represented as a log(n) bit counter) and generates bits based on this
counter.

Big difference is that a separate decorrelator has the
non-deterministic output outside of the S/D feedback loop...

It's probably time to let this sit a bit and/or do some simulations.


 


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