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Fri Jul 29 09:50:46 EDT 2016

Compilation regexp broke

Maybe first limit it a little.

(pp-eval-expression 'compilation-error-regexp-alist)

(vhdl-directory vhdl-advance-ms vhdl-advance-ms-file vhdl-aldec vhdl-cadence-leapfrog vhdl-cadence-nc vhdl-ghdl vhdl-ibm-compiler vhdl-ikos vhdl-ikos-file vhdl-modelsim vhdl-leda-provhdl vhdl-quartus vhdl-quickhdl vhdl-savant vhdl-simili vhdl-speedwave vhdl-synopsys vhdl-synopsys-design-compiler vhdl-synplify vhdl-vantage vhdl-vantage-file vhdl-veribest vhdl-viewlogic vhdl-viewlogic-file vhdl-xilinx-xst vhdl-directory vhdl-advance-ms vhdl-advance-ms-file vhdl-aldec vhdl-cadence-leapfrog vhdl-cadence-nc vhdl-ghdl vhdl-ibm-compiler vhdl-ikos vhdl-ikos-file vhdl-modelsim vhdl-leda-provhdl vhdl-quartus vhdl-quickhdl vhdl-savant vhdl-simili vhdl-speedwave vhdl-synopsys vhdl-synopsys-design-compiler vhdl-synplify vhdl-vantage vhdl-vantage-file vhdl-veribest vhdl-viewlogic vhdl-viewlogic-file vhdl-xilinx-xst vhdl-directory vhdl-advance-ms vhdl-advance-ms-file vhdl-aldec vhdl-cadence-leapfrog vhdl-cadence-nc vhdl-ghdl vhdl-ibm-compiler vhdl-ikos vhdl-ikos-file vhdl-modelsim vhdl-leda-provhdl vhdl-quartus vhdl-quickhdl vhdl-savant vhdl-simili vhdl-speedwave vhdl-synopsys vhdl-synopsys-design-compiler vhdl-synplify vhdl-vantage vhdl-vantage-file vhdl-veribest vhdl-viewlogic vhdl-viewlogic-file vhdl-xilinx-xst vhdl-directory vhdl-advance-ms vhdl-advance-ms-file vhdl-aldec vhdl-cadence-leapfrog vhdl-cadence-nc vhdl-ghdl vhdl-ibm-compiler vhdl-ikos vhdl-ikos-file vhdl-modelsim vhdl-leda-provhdl vhdl-quartus vhdl-quickhdl vhdl-savant vhdl-simili vhdl-speedwave vhdl-synopsys vhdl-synopsys-design-compiler vhdl-synplify vhdl-vantage vhdl-vantage-file vhdl-veribest vhdl-viewlogic vhdl-viewlogic-file vhdl-xilinx-xst vhdl-directory vhdl-advance-ms vhdl-advance-ms-file vhdl-aldec vhdl-cadence-leapfrog vhdl-cadence-nc vhdl-ghdl vhdl-ibm-compiler vhdl-ikos vhdl-ikos-file vhdl-modelsim vhdl-leda-provhdl vhdl-quartus vhdl-quickhdl vhdl-savant vhdl-simili vhdl-speedwave vhdl-synopsys vhdl-synopsys-design-compiler vhdl-synplify vhdl-vantage vhdl-vantage-file vhdl-veribest vhdl-viewlogic vhdl-viewlogic-file vhdl-xilinx-xst vhdl-directory vhdl-advance-ms vhdl-advance-ms-file vhdl-aldec vhdl-cadence-leapfrog vhdl-cadence-nc vhdl-ghdl vhdl-ibm-compiler vhdl-ikos vhdl-ikos-file vhdl-modelsim vhdl-leda-provhdl vhdl-quartus vhdl-quickhdl vhdl-savant vhdl-simili vhdl-speedwave vhdl-synopsys vhdl-synopsys-design-compiler vhdl-synplify vhdl-vantage vhdl-vantage-file vhdl-veribest vhdl-viewlogic vhdl-viewlogic-file vhdl-xilinx-xst verilog-leda verilog-verilator verilog-vcs-4 verilog-vcs-3 verilog-vcs-2 verilog-vcs-1 verilog-xsim verilog-verbose verilog-surefire-2 verilog-surefire-1 verilog-IES verilog-xl-2 verilog-xl-1 vhdl-directory vhdl-advance-ms vhdl-advance-ms-file vhdl-aldec vhdl-cadence-leapfrog vhdl-cadence-nc vhdl-ghdl vhdl-ibm-compiler vhdl-ikos vhdl-ikos-file vhdl-modelsim vhdl-leda-provhdl vhdl-quartus vhdl-quickhdl vhdl-savant vhdl-simili vhdl-speedwave vhdl-synopsys vhdl-synopsys-design-compiler vhdl-synplify vhdl-vantage vhdl-vantage-file vhdl-veribest vhdl-viewlogic vhdl-viewlogic-file vhdl-xilinx-xst absoft ada aix ant bash borland python-tracebacks-and-caml comma cucumber msft edg-1 edg-2 epc ftnchek iar ibm irix java jikes-file maven jikes-line gcc-include ruby-Test::Unit gnu lcc makepp mips-1 mips-2 msft omake oracle perl php rxp sparc-pascal-file sparc-pascal-line sparc-pascal-example sun sun-ada watcom 4bsd gcov-file gcov-header gcov-nomark gcov-called-line gcov-never-called perl--Pod::Checker perl--Test perl--Test2 perl--Test::Harness weblint)


Looks like the vhdl mode adds to the variable on every compile.

(absoft ada aix ant bash borland python-tracebacks-and-caml comma cucumber msft edg-1 edg-2 epc ftnchek iar ibm irix java jikes-file maven jikes-line gcc-include ruby-Test::Unit gnu lcc makepp mips-1 mips-2 msft omake oracle perl php rxp sparc-pascal-file sparc-pascal-line sparc-pascal-example sun sun-ada watcom 4bsd gcov-file gcov-header gcov-nomark gcov-called-line gcov-never-called perl--Pod::Checker perl--Test perl--Test2 perl--Test::Harness weblint)


compilation-mode-hook
(vhdl-error-regexp-add-emacs verilog-error-regexp-add-emacs)


Maybe clearing compilation-mode-hook will solve it?




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