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Wed Aug 3 00:09:39 EDT 2016

setup and hold time

http://www.edn.com/design/analog/4371393/Understanding-the-basics-of-setup-and-hold-time

Fundamental to operation is the 2-latch structure.
Clock = 0 : first pass, second latches
Clock = 1 : first latches, second passes

Question: if the output feeds back to the input through a
combinatorial circuit with a propagation delay less than the setup
time, isn't that a problem?

Or is the propagation delay through the second phase always more than
the hold time?

From this:
http://www.cs.wustl.edu/~roger/260M.f13/CSE260M-Timing.pdf

It seems that indeed hold time violations can occur if the
combinatorial circuit is too fast.  But it says also:

  In FGPAs, it is often the case that hold time < (min FF prop. delay)
  – (max clock skew) so, hold time violations cannot occur




Prose:

So I started digging into the reason why sequential logic actually
works, e.g. why it is possible that you can drive a FF with a signal
that is derived from another FF.  This seems nonsensical if you look
at the whole metastable problem, where you don't sample when somebody
else is writing because it causes setup and hold time violations.
Now, why then would a signal that changes on an edge be fed into a FF
that samples on the same edge?  Makes no sense right?  Paradox.

The reason is: For FF feeding into FF, e.g. in a shift register, the
propagation delay to the output of the FF ensures that the hold time
on the input is not violated.

So the fact that propagation delay is finite and larger than the hold
time is actually _essential_ to how these things work.




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