Mon Aug 1 13:50:19 EDT 2016
SPI has 4 possible modes for clock/data polarity, and two of them
dominate -- almost all SPI devices update their MISO output on the
falling edge of a clock and read their MOSI input on the rising
edge of a clock.
So if there is a choice, pick:
- write edge 1->0
- read edge 0->1
and pick write edge before read edge, so idle=1
Implementing CPHA=1 in hardware is easy: write edge comes before read
CHPH=0 is harder because the first write edge is actually
non-existant, and the last clock edge in a transfer is not used. Data
needs to be set up before the first clock arrives.
If bit 0 needs to be written by a slave, it should be written when CS
However it seems that for many slave devices, the packet data has a
request/reply structure, meaning the bits corresponding to the command
traveling in the other direction are dont-care.