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Mon Jun 20 15:39:04 EDT 2016

metastability and derived clocks

72MHz STM32 clock -> 36MHz FPGA clock (STM32 timer).

There might be a problem with this as signals generated by STM32 will
change state at exactly the same time as the main FPGA clock edge.

So if FPGA is clocked on posedge of timer, and bus writes are on
posedge as well, we have an issue...

If this is a problem, inverting the clock would fix it.




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