Fri Jun 10 13:19:53 EDT 2016
Implementing SPI: some design considerations.
1. Determine whether to clock the SPI state machine from the external
or the internal clock.
"Since the SPI bus is typically much slower than the FPGA
operating clock speed, we choose to over-sample the SPI bus using
the FPGA clock. That makes the slave code slightly more
complicated, but has the advantage of having the SPI logic run in
the FPGA clock domain, which will make things easier afterwards."
It seems best to follow this setup.
If SPI clock is in a different clock domain than main clock, add
synchronizer FFs to clock and serial in.
2. State transitions