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Tue Feb 2 22:16:32 EST 2016

VHDL

architecture:
- structure:  instantiate components, map ports (schematics)
- dataflow:   . <= . <op> .  (signal propagation)
- behavioral: based on sequential processes (abstracted from implementation)
- rtl:        ..


Processes execute top to bottom, triggered by events in the
sensitivity list.  It is important not to confuse variables and
signals, as described in [2].


[1] http://gmvhdl.com/VHDL.html
[2] http://www.gmvhdl.com/signals.htm




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